1. Technical Field
The present invention relates to an electronic component assembly, an electronic component having solder bumps, and processes for producing such assembly and component. More particularly, the present invention relates to the electronic component assembly and the electronic component having solder bumps, each of which is characterized by a concave portion being provided on a surface of the electronic component. And also, the present invention particularly relates to a process for producing the electronic component assembly and the electronic component having solder bumps, by the use of an electronic component whose surface is provided with a concave portion.
2. Description of the Related Art
With a development of high density and high integration of a semiconductor integrated circuit (LSI) used for electronics device, higher pin count and finer pitch of electrodes of LSI chip have been rapidly developed in recent years. The LSI chip is mounted over a circuit substrate by generally performing a flip-chip mounting process in order to decrease wiring delay. It is a common practice in this flip-chip mounting process to form solder bumps on the electrodes of the LSI chip, and then connect, through such solder bumps, all the electrodes of the LSI chip to all electrodes formed on the circuit substrate in a batch process.
For mounting a next-generation LSI having 5000 or more electrodes over the circuit substrate, it is required to form fine-pitch bumps with its pitch of 100 μm or less. It is, however, difficult for a conventional solder bump forming process to form such fine-pitch bumps. Moreover, from a viewpoint that a large number of bumps must be formed depending on the number of the electrodes, a reduction of the mounting tact time per chip is required for reducing a manufacturing cost.
Conventionally, there has been developed a plating process and a screen printing process as a bump forming process. The plating process is convenient for achieving the fine pitch, but it is complicated and has to compromise the productivity. The screen printing process, on the other hand, has a high productivity, but is not convenient for achieving the fine pitch since the use of a mask is required.
Recently, there has been developed several processes for selectively forming solder bumps on electrodes of the LSI chip or circuit substrate. These processes are not only convenient for forming fine bumps, but also convenient for achieving a high productivity since a plurality of the fine bumps can be formed in a batch process. Accordingly they are expected as promising processes that can be applicable to the mounting of the next-generation LSI over the circuit substrate.
According to one of these promising processes, there is a solder paste process (for example, see Japanese Patent Kokai Publication No. 2000-94179 which is referred to also as “Patent literature 1”). In this process, a solder paste comprising a mixture of metal particles and a flux is applied directly onto a substrate having electrodes thereon, and subsequently the substrate is heated so as to melt the metal particles. As a result, the solder bumps are formed selectively on the electrodes due to the wettability thereof.
There is also another process called as a super solder paste process wherein a paste composition (“deposition type solder using chemical reaction”) mainly comprising organic acid lead salt and tin metal is applied directly onto a substrate having electrodes thereon, and subsequently the substrate is heated so as to induce a displacement reaction for Pb and Sn, and thereby Pb/Sn alloy is selectively deposited on electrodes of the substrate. For example, see Japanese Patent Kokai Publication No. H01-157796 (which is referred to also as “Patent literature 2”).
In both of the solder paste process and the super solder paste processes, the paste composition is applied onto the substrate and thus a local variation in thickness and the solder concentration of the applied composition is occurred. This causes the deposition amount of the solder to differ from one electrode to another, and therefore their processes cannot form bumps which are all equal in height. As to such processes, the paste composition is applied onto the substrate of which surface is not smooth due to the electrodes formed thereon (namely, electrode-forming regions form convex portions whereas no electrode-forming regions form recess portions). As a result, an insufficient amount of the solder is supplied on the electrodes having a higher level than that of the substrate surface, and thus it is difficult to form the bumps with satisfactory heights required for the flip-chip mounting.
By the way, as for a flip-chip mounting process employing a conventional bump forming technique, subsequent to mounting a semiconductor chip over a circuit substrate having bumps formed thereon, it is required that a resin (which is called “underfill”) is poured into a clearance gap formed between the circuit substrate and the semiconductor chip so as to secure the semiconductor chip to the circuit substrate.
There has been developed a process making it possible to perform not only an electrical connection between the electrodes of the semiconductor chip and the electrodes of the circuit board, but also a securing of the semiconductor chip to the circuit substrate. For example, according to a process disclosed in Japanese Patent Kokai Publication No. 2000-332055 (which is referred to also as “Patent literature 3”), a flip-chip mounting is performed with the use of an anisotropic electrically conductive material. In this process, a thermosetting resin comprising electrically conductive particles is supplied between the circuit substrate and the semiconductor chip, and subsequently the semiconductor chip is pressed and at the same time the thermosetting resin is heated. As a result, the electrical connection between the electrodes of the semiconductor chip and the circuit substrate, and the securing of the semiconductor chip to the circuit substrate are concurrently achieved. The anisotropic electrically conductive material is available for the connection between circuit boards as well as for the connection between the semiconductor chip and the circuit board.
However, in the case of the above flip-chip mounting process using the anisotropic conductive material, an electrical conduction between the opposing electrodes is achieved due to a mechanical contact through the electrically conductive particles, and thus a stability of the electrical conduction is hard to maintain.
That is to say, considering an applicability to the next-generation LSI chip having 5000 or more electrodes, the flip-chip mounting process using the anisotropic conductive material has lots of problems in terms of productivity and reliability. There are similar problems with the connection between circuit boards, which must meet the requirements for smaller pitch, larger number of pins and higher reliability.
Recently, novel processes of forming solder connections or solder bumps by making use of self-congregating solder technique have been proposed as the flip-chip mounting process and solder bump forming process that can be applied to the next-generation LSI. For example, see Japanese Patent Kokai Publication No. 2006-100775 (which is referred to also as “Patent literature 4”) and Japanese Patent Kokai Publication No. 2006-114865 (which is referred to also as “Patent literature 5”). With this technique, solder connections or solder bumps are formed on electrodes through self-congregation or aggregation of solder powder thereonto.                Patent literature 1: Japanese Patent Kokai Publication No. 2000-94179        Patent literature 2: Japanese Patent Kokai Publication No. H01-157796        Patent literature 3: Japanese Patent Kokai Publication No. 2000-332055        Patent literature 4: Japanese Patent Kokai Publication No. 2006-100775        Patent literature 5: Japanese Patent Kokai Publication No. 2006-114865        Patent literature 6: Japanese Patent Kokai Publication No. 2004-260131        Non-patent literature 1: 10th Symposium on “Microjoining and Assembly Technology in Electronics” Feb. 5-6, 2004, pp. 183-188        Non-patent literature 2: 9th Symposium on “Microjoining and Assembly Technology in Electronics” Feb. 6-7, 2003, pp. 115-120        